1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a main memory portion and a sub-memory portion formed in a semiconductor substrate and a data transfer circuit provided between the main memory portion and the sub-memory portion, and particularly, to a semiconductor integrated circuit device which can reduce its internal operating frequency.
This application is based on Japanese Patent Application No. 11-67556, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In general, a relatively low speed, inexpensive semiconductor device having large memory capacity, such as general purpose DRAM, is used as the main memory in a computer system.
In the recent computer systems, the operating speed of a DRAM constituting the main memory increases with an increase in an operating speed of the system, particularly, of the MPU thereof. However, the operating speed of the DRAM is still insufficient and, in order to solve this problem, it is usual to provide a sub-memory between the MPU and the main memory. Such sub-memory is generally called as a cache memory and is constructed with a high speed SRAM or an ECLRAM.
The cache memory is generally provided to the MPU externally or internally. Recently, a semiconductor device in which the DRAM constituting the main memory and the cashe memory are mounted on the same semiconductor substrate have gained attention. Japanese Unexamined Patent Application, First publication Nos. Sho 57-20983, Sho 60-7690, Sho 62-38590 and Hei 1-146187 disclose examples of such semiconductor memory. Such semiconductor memory is sometimes called a cache DRAM or CDRAM since it includes the DRAM and the cache memory. Data are bi-directionally transferred between the SRAM, which functions as the cashe memory, and the DRAM which is the main memory.
Recently, in the semiconductor integrated circuit devices, as the data reading speed increases, the operating frequency has also increased. The operating frequency of the semiconductor memory device such as a DRAM depends on the operating frequency of the internal circuits such as address buffers and decoders. Therefore, unless the operating frequency of the internal circuits is increased, the operating frequency of the entire device cannot be increased, and the device cannot handle further increases in speed.
This problem will be specifically discussed with reference to FIGS. 64 and 65.
FIG. 64 shows a construction of a data read block of a conventional semiconductor memory device. In this example, an SRAM column address signal iASC, which is generated from an external address is input from the outside, is input via a column address buffer 392J to a column decoder 390J. The column decoder 390J decodes the signal and inputs an SRAM column decoded output signal SSL to an SRAM array 120J. In the SRAM array 120J, data buffers 394J which include SRAM cells are arranged in a matrix, and the respective data buffers 394J have switch circuits 397J which become conductive depending on the SRAM column decoded output signals SSL from the column decoder 390J. The respective data buffers 394J are connected via the switch circuits 397J to a data input/output line SIO. The data input/output line SIO is connected to a data control circuit 160J which includes a data latch circuit 395J and a data-out buffer 152J. The SRAM column decoder 123J and the data control circuit 160J are operated synchronously with an external clock signal (CLK) which is not shown.
According to this construction, in every clock cycle of the external clock signal CLEK, the SRAM column address signals iASC are successively generated corresponding to addresses A0 to A3. The column decoded output signals SSL corresponding to the addresses A0 to A3 are successively generated in every clock cycle, and are delayed from the SRAM column address signal iASC by a half of one clock cycle. Data D0 to D3 from the data buffers 394J, which are specified by the SRAM column decoded output signals SSL, successively appear at the data input/output line SIO in every clock cycle. The data control circuit 160J inputs these signals, and outputs the signals as data DQ in every clock cycle.
In this conventional technique, the internal circuits such as the column decoder and the data control circuit complete one operation within one clock cycle, that is, the operating frequency for reading the data depends on the operating frequency of the internal circuits.
Document "400 MHz Random Column Operating SDRAM Techniques with Self Skew Compensation", 1997, Symposium on VLSI Circuits Digest of Technical Papers, pp105-106, discloses a technique for improving the operating frequency using a multi-line data read path from a memory array. While this technique accelerates the operation in the data transfer path downstream from the DRAM memory array, the technique restricts the operating frequency of an address transfer path (such as an address buffer, a column decoder, and a data bus) from inputting of an external address to specifying of a memory cell because this path is constructed in a manner similar to the conventional devices. This technique includes adding a plurality of switches and a plurality of local IO lines to respective sense amplifiers for providing the multi-line data transfer path for the DRAM, and therefore the overhead in layout may be increased.